[Bioclusters] what motherboards are people using for dual Athlon boxes?

[Joseph Landman]

On Thu, 2003-03-06 at 09:28, Steve Gaudet wrote:

> Other consideration for Intel is Hyperthreading, and the new 7501 chipset
> will deliver at least 80% from the second cpu...depending on your code.

Various testing on the OpenMosix list (and several other places)
contradicts this on "real" codes.  The best I have heard out of a real
code is about 30%, and the nominal is closer to -5 to -10%.  This is the
case to the point that systems manufacturers are starting to ship HT
threading turned off in the bios.

> Some people won't consider Intel because they don't want to rework their
> code.  Understandable, however, those that do see the benefits of the new
> Xeon over Athlon.  Some of our customers have seen close to 90% unitization
> from the second cpu with the 7501 chipset when their code is performance
> tuned.

Possibly on an SMP, and that would be nice to see on this platform. 
Unlikely on HT.  For BLAST however, the Athlon does nicely, and the -j 2
switch gives you 50-90% additional performance (search and algorithm
dependent) from what I have tried myself on non-pathological cases.

The nice aspect about the Athlon is that you get the performance without
reworking the code.  Using the nForce2 MB I got a 30% boost in memory
bandwidth, which translated to something around 30% on some of the codes
I was working on.  It was about a 10% better performer on BLAST than the
KT266a.  I don't have easy access to a 3+ GHz P4, or a 2800+ AMD Athlon,
or an Opteron, so I cannot do a BLAST comparison at this time with the
really new stuff.  The older P4's needed more than a 500+MHz clock speed
advantage to near the performance of the older Athlons.  If I can get my
hands on some of the newer stuff, I will run some tests (blastx of a
large set of ests vs nr).  

I think the HT support needs to mature for it to be of signficant value,
though as with everything, your mileage will vary.  The PPC vector
support is interesting in how easy it is to integrate into existing
codes.  I would like to see this with SSE2/MMX2 for x86 stuff.

-- 
Joseph Landman, Ph.D
Scalable Informatics LLC
email: landman@scalableinformatics.com
  web: http://scalableinformatics.com
phone: +1 734 612 4615