Hi Farul: On Fri, 13 Jan 2006 22:46:04 +0800, Farul Mohd. Ghazali wrote > Some years back when Timelogic and Paracel were popular there were > some discussions on FPGA based computing for Linux clusters. I can't > recall if there was a general conclusion but one of the limitations > was that you're stuck with the algorithms the manufacturer provided. In some cases this is true (TimeLogic, et al: Paracel went under). The reality of today is quite different for board based units. There you can use any number of technologies to map your algorithm to the card. > SGI approached me recently to talk about their reconfigurable FPGA > systems and I was intrigued. The new RASC allows a user to remap the > FPGA according to your own algorithms instead of being limited to one > set of libraries. They also link it with GNU tools for debugging etc. This isn't restricted to SGI. There are folks selling C to VHDL/Verilog compilers out there. You will not get as good performance as hand designing the circuit, but it is certainly a start. Think of it like the old autoparallelizers. They didn't give you linear speedups. What they did is give you "good enough" in many cases, or got you started on your way to accelerate more. > Has anyone looked at the SGI RASC or any other equivalent system out > there? Any ideas if it makes sense in today's clusters? The workload <bias alert> I would avoid things that look proprietary to vendors whom are not doing so well in the market. Unless the thing is open and available from others when and if SGI goes away, that is a good enough reason to look at similar technology from open vendors. We work with a company that designs and builds such cards and software. If you are interested, we can get you more info. This would be for offline so as not to spam everyone. </bias> > I'm supporting has very few custom written algorithms and is mostly > BLAST, phred/phrap, hmmer with some heavy Amber and Gromacs thrown in > as well. Today, accelerating integer apps (SW, HMMer, MSA) isn't too painful on "commodity" accelerator cards (available over the counter). The cards plus software will run into a little money (about 2-4 compute nodes worth), but give you stellar performance (10-100 compute nodes worth). Accelerating floating point intensive applications cannot easily be done today on FPGA's, as FPGA's don't have enough gates for lots of IEEE754/854 units. This will change over time, but it will take a while. If you can live with non-IEEE math (you need to think over the implications of this very carefully), you have many options, some of which are terribly interesting. That said, some very interesting things are on the horizon that should address Amber and Gromacs among other dynamics codes. Joe > > TIA. > _______________________________________________ > Bioclusters maillist - Bioclusters at bioinformatics.org > https://bioinformatics.org/mailman/listinfo/bioclusters -- Scalable Informatics LLC http://www.scalableinformatics.com phone: +1 734 786 8423